1. Field of the Invention
The present invention relates to an organic light emitting display having a polycrystalline silicon thin film transistor (“TFT”), a method of fabricating the same, and an organic light emitting display including the transistor.
2. Description of the Related Art
Active color image display apparatuses using an organic light emitting diode (“OLED”) generally use a circuit including two transistors and one capacitor. In particular the circuit includes a switching transistor (also known as a sampling transistor), which provides an analog image signal, a memory capacitor retaining an image signal and a driving transistor controlling a current supplied to an OLED according to an image signal voltage accumulated on the memory capacitor. This circuit has what is called a 2T-1C structure, wherein the “2T” stands for two transistors and the −“1C” represents one capacitor, and an example of such circuit construction is disclosed in Japanese Patent Laid-open Publication No. 2002-156923. A pixel including a 2T-1C structure can be constructed using a complementary metal-oxide-semiconductor (“CMOS”) obtained from a wafer which comprises single crystalline silicon. However such a pixel cannot be easily constructed using a thin film transistor (“TFT”) structure.
An n-channel polycrystalline silicon TFT is used in manufacturing an OLED on a glass or plastic substrate. The advantage of using polycrystalline silicon is that it is able to obtain very high charge carrier mobility compared to amorphous silicon. However, the disadvantage of using polycrystalline silicon is that it may have a high leakage current when turned off.
It is well known that, in such a polycrystalline silicon TFT, leakage of a current is generated in a depletion region of a drain by grain boundary traps (see Ferry G. Fossum, et al., IEEE Trans. Electron Devices, vol. ED-32, pp. 1878-1884, 1985).
In order to more effectively reduce current leakage, an offset structure has been proposed (see M. Rodder et al., IEEE Electron Device Letters, Vol. EDL-6, No. 11, November 1985). An offset region is located between a channel and a gate and another offset region is located between the channel and the drain. The use of offsets deteriorates an electric field generated at the drain and reduces field emission caused by a gate voltage and a drain voltage. However, in the prior art, a doping process which varies locally is required to form an offset structure. Unfortunately this locally varying doping process requires the use of an additional mask in order to manufacture the offset structure. In order to successfully perform differential doping in the offset region using the mask, the mask is required to be precisely aligned on a substrate. However, since the manufacturing method uses an additional mask, a doping process is complicated, yield is low and productivity is degraded.
Accordingly, a simplified method of manufacturing a transistor having an offset structure is required. In particular, the number of masks required for the formation of a lowly doped drain (“LDD”) is required to be minimized.